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Digital Phase Follower -- Deserializer in Low-Cost FPGA презентация
Содержание
- 1. Digital Phase Follower -- Deserializer in Low-Cost FPGA
- 2. Motivation In HEP systems, sometime many channels
- 3. Receiving Serial Data Data channels are de-serialized
- 4. Multiple Sampling Multiple sampling is used to
- 5. More Notes on Multiple Sampling In digital
- 6. Digital Phase Follower, Block Diagram
- 7. Digital Phase Follower: Operation
- 8. Was 0, Is 3, Data Is Slower.
- 9. Was 3, Is 0, Data Is Faster.
- 10. Simulation (1) This is a 4B/5B receiver
- 11. Simulation (2) The same receiver running with
- 12. Deserializer Based on Digital Phase Follower Data
- 13. Digital Phase Follower Start-up Preamble: 1 idle
Motivation In HEP systems, sometime many channels of serial data must be concentrated. It will be nice if the data clock is not transmitted separately. (Just transmit a single data channel).
Слайд 2Motivation
In HEP systems, sometime many channels of serial data must be
concentrated.
It will be nice if the data clock is not transmitted separately. (Just transmit a single data channel).
It will be nice if it can be received in low-cost FPGA in which dedicated serial data receivers are not available.
It will be nice if user protocol can be supported. (Can be 8B/10B, or can be anything users want).
Examples:
TSO modules to PP modules. (500 Mbps, user protocol).
FPIX2 to PDCB. (140 Mbps, user protocol).
It will be nice if the data clock is not transmitted separately. (Just transmit a single data channel).
It will be nice if it can be received in low-cost FPGA in which dedicated serial data receivers are not available.
It will be nice if user protocol can be supported. (Can be 8B/10B, or can be anything users want).
Examples:
TSO modules to PP modules. (500 Mbps, user protocol).
FPIX2 to PDCB. (140 Mbps, user protocol).
Слайд 3Receiving Serial Data
Data channels are de-serialized using shift registers.
The clock for
the receiving shift registers comes from:
Separate channel. (Channel-channel skew ☹ ).
Same data channel.
Clock recovery using PLL. (Phase detection+VCO).
Dynamic phase aligner. (In Altera devices, choosing a correct clock phase from 8 phase samples).
Digital phase follower. (For low-cost FPGA).
Separate channel. (Channel-channel skew ☹ ).
Same data channel.
Clock recovery using PLL. (Phase detection+VCO).
Dynamic phase aligner. (In Altera devices, choosing a correct clock phase from 8 phase samples).
Digital phase follower. (For low-cost FPGA).
Слайд 4Multiple Sampling
Multiple sampling is used to determine the phase of the
data.
A correct sampling point is automatically chosen after first 0 to 1 transaction.
The sampling point shifts following the shift of the data phase.
Everything is in standard digital circuit.
A correct sampling point is automatically chosen after first 0 to 1 transaction.
The sampling point shifts following the shift of the data phase.
Everything is in standard digital circuit.
b0
b1
b2
b0
b1
b2
b3
b0
b1
b2
b3
b4
b5
Quad Sampling
Fs = 4/UI
Triple Sampling
Fs = 3/UI
Double Sampling
Fs < or > 2/UI
Слайд 5More Notes on Multiple Sampling
In digital phase follower, since no clock
recovery is needed, 4, 3 or 2 samples per bit (unit interval) are sufficient. (Not 8).
In double sampling case, sampling rate must be known either less or larger than 2/UI.
In double sampling case, sampling rate must be known either less or larger than 2/UI.
b0
b1
b2
b0
b1
b2
b3
b0
b1
b2
b3
b4
b5
Quad Sampling
Fs = 4/UI
Triple Sampling
Fs = 3/UI
Double Sampling
Fs < or > 2/UI
Слайд 6Digital Phase Follower, Block Diagram
c0
c90
c180
c270
c0
Data In
Multiple
Sampling
Clock
Domain
Changing
b0
b1
Frame
Detection
Data
Out
Tri-speed
Shift
Register
Shift2
Shift0
was3
is0
SEL
was0
is3
Trans.
Detection
Q0
Q1
Q2
Q3
QF
QE
QD
Слайд 7Digital Phase Follower: Operation
b0
SEL
Q0
Q1
Q2
Q3
QF
QE
QD
Newer Samples
Older Samples
Selected
Sample
Selected
Sample
Selected
Sample
Selected
Sample
SEL=0
SEL=1
SEL=2
SEL=3
Слайд 8Was 0, Is 3, Data Is Slower. Shift 0.
Q0
Q1
Q2
Q3
QF
QE
QD
Old
Selection
New
Selection
SEL was 0
SEL
is 3
b0
b1
Tri-speed
Shift
Register
Shift2
Shift0
was3
is0
SEL
was0
is3
Q0
Q1
Q2
Q3
This bit has been sent to the shift register. No duplicate recording.
Newer Samples
Older Samples
Слайд 9Was 3, Is 0, Data Is Faster. Shift 2.
Q0
Q1
Q2
Q3
QF
QE
QD
New
Selection
Old
Selection
SEL was 3
SEL
is 0
b0
b1
Tri-speed
Shift
Register
Shift2
Shift0
was3
is0
SEL
was0
is3
Q0
Q1
Q2
Q3
This bit has not been sent to the shift register. Sent it through b1, along with new selection b0=Q0.
Newer Samples
Older Samples
Слайд 10Simulation (1)
This is a 4B/5B receiver working at 400Mbps, compiled in
an Altera Cyclone device.
The receiving clock is 0.4% slower – no errors is seen.
The receiving clock is 0.4% slower – no errors is seen.
Слайд 11Simulation (2)
The same receiver running with receiving clock 0.4% faster –
no errors is seen.
Слайд 12Deserializer Based on Digital Phase Follower
Data is self-timed, no separate clock
transmission is needed.
The transmitter and receiver clocks can be independent – frequency difference is compensated.
User protocols are supported.
It can be implemented in low-cost FPGA.
The transmitter and receiver clocks can be independent – frequency difference is compensated.
User protocols are supported.
It can be implemented in low-cost FPGA.
Слайд 13Digital Phase Follower Start-up
Preamble: 1 idle word with 0 to 1
transitions.
In other scheme, long preambles or training patterns are needed.
Frame detection: defined by user. It can be 10000000000000xxxxxxxxxx (in FPIX2).
Data:
In other scheme, long preambles or training patterns are needed.
Frame detection: defined by user. It can be 10000000000000xxxxxxxxxx (in FPIX2).
Data:
