Changes to LPDIMM Rev 02_r1 презентация

Antena via (47 Dangling, 620 Antena). – one dangling line left

B. clean unneeded shapes.

C. move vias in all design so they will not be on shape’s edge (example in section 6)

are routed too close (touching) in voids of the reference plane above it or beneath.
In the pic at following page, there is example of this case in L3 routing, with reference in L2_GND.
It is wanted that lines will be far from these voids 1W (one signal width), but at least not touching if 1W is not possible.

Keepin.

will contain all vias only in the DRAM BGA TOP layer.

layer6 according to below.

L5 and bottom next to (672.000 -130.000)

mask and leave C_VDDQX_VR_CSP plane open from SM.

SM

Open from SM

Open from SM

SM

in U9 us connected to C_VDDQX_VR_CSP plane with a small shape in the bottom.
Convert the connection to normal trace and not a plane with 1 via.
The same for pin #7 (VCC_0V6_VDDQX plane)

and move the GND vias).
Enlarge VCC_1V1_0V6_VDDQ_DRAM plane so the vias connected to it from resistor R41 will be inside the plain and not on the edge.

near R40

TP instead of direct connection to the plane.

If impossible, try at least to do that for 1.1V (TP11 and TP15)

that moved.
Fix silk of TP that moved.
Change card name (LPDIMM_LP4_200B) to: LP4/x_200B (CNL U) – move to Bottom.

PN to: J24748-001 (leave Rev 01).
Change ASSY PN to: J24748-100

J6, R27.
Please move J5 (4 pin header) a little to the right.
Place new components in the red square area.

It doesn’t have to be exactly like I requested. It can be changed a little bit as long as everything fit.